Hardware and software co-design in space compaction of cores-based digital circuits

The implementation of a fault testing environment for embedded cores-based digital circuits is a challenging endeavor. The subject paper aims at developing techniques in design verification and test architecture, utilizing well-known concepts of hardware and software co-design. There are available methods to ensure correct functionality, in both hardware and software, for embedded cores-based systems but one of the most used and acceptable approaches to realize this is through the use of design for testability. Specifically, applications of the built-in self-test (BIST) methodology in testing embedded cores are considered in the paper, with specific implementations being targeted towards ISCAS 85 combinational benchmark circuits.