Yield evaluation methods of SRAM arrays: a comparative study

With the increasing needs for memory testing and repair, yield evaluation is an essential decision-making factor to define redundancy allocation and testing strategies. In particular, yield evaluation can resolve the many issues revolving around cost-effective BIST solutions and purely ATE based techniques to guarantee higher test transparency. In this document, two different yield calculation methodologies for SRAM arrays are presented. General yield calculation formulas for VLSI chips are initially presented. The regular repetitive structure of a RAM array is considered because it shows major yield improvements with the introduction of redundancy. Two repair yield evaluation formulas for a 1D redundant array are introduced and compared; the first one is based on Markov modeling, the second one is based on an approximation.