Test methodology for low power VLSI neural oscillator circuit

This paper presents new test and verification methodologies, including design techniques targeting a neural oscillator. Because the output signal of a neuron is chaotic, customized verification and test methodologies are required. We have chosen to use MATLAB to verify our experimental results at a simulation level. In this paper we also describe a test circuit used to perform electronic neuron IC testing. We investigate how a subthreshold circuit can reduce power consumption. In our HSPICE simulations, we both validate the proposed test circuit and verify the electronic neuron and synapse circuit.