Title :
A differential summing amplifier for analog VLSI systems
Author :
Titus, A.H. ; Gopalan, A.
Author_Institution :
Dept. of Electr. Eng., Univ. at Buffalo, NY, USA
Abstract :
We have designed, fabricated and tested an analog VLSI version of a differential summing amplifier that is based on the differential difference amplifier. This is a four-input amplifier with twelve minimal-sized transistors that covers an area that is 120 times less than previous differential difference amplifier designs, which makes it ideally suited for smart-pixel focal-plane arrays or analog neural networks that require high-density analog components of minimal size. The circuit has been tested and compared to larger versions using a chip fabricated through MOSIS using the AMI 1.5 μm two metal layer, double-poly analog process in a 2.2 mm×2.2 mm tiny chip padframe. The experimental results show that its operation is favorable with the larger versions for use in open-loop mode, as a voltage follower, or output level-shifter.
Keywords :
VLSI; analogue integrated circuits; differential amplifiers; integrated circuit design; integrated circuit packaging; integrated circuit testing; operational amplifiers; summing circuits; 1.5 micron; 2.2 mm; AMI two metal layer double-poly analog process; MOSIS fabrication; amplifier area; analog VLSI systems; analog neural networks; chip padframe; circuit test; differential difference amplifier; differential summing amplifier; four-input amplifier; high-density analog components; minimal-sized transistors; open-loop mode voltage follower; output level-shifter; smart-pixel focal-plane arrays; Circuit testing; Detectors; Differential amplifiers; Intelligent actuators; Intelligent sensors; Microactuators; Microsensors; Sensor arrays; Very large scale integration; Voltage;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010387
