A differential summing amplifier for analog VLSI systems

We have designed, fabricated and tested an analog VLSI version of a differential summing amplifier that is based on the differential difference amplifier. This is a four-input amplifier with twelve minimal-sized transistors that covers an area that is 120 times less than previous differential difference amplifier designs, which makes it ideally suited for smart-pixel focal-plane arrays or analog neural networks that require high-density analog components of minimal size. The circuit has been tested and compared to larger versions using a chip fabricated through MOSIS using the AMI 1.5 μm two metal layer, double-poly analog process in a 2.2 mm×2.2 mm tiny chip padframe. The experimental results show that its operation is favorable with the larger versions for use in open-loop mode, as a voltage follower, or output level-shifter.