• DocumentCode
    1804619
  • Title

    Memory exploration utilizing scheduling effects in high-level synthesis

  • Author

    Seo, Jaewon ; Kim, Taewhan

  • Author_Institution
    Dept. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol., South Korea
  • Volume
    4
  • fYear
    2002
  • fDate
    2002
  • Abstract
    In this paper, we address one critical limitation of the previous work on the problem of memory exploration in high-level synthesis, namely, a tight coupling of scheduling effects with memory exploration, that has been ignored by most existing memory synthesis systems. To overcome the limitation, we propose an integrated approach that takes into account the memory configurations and schedules simultaneously. Experimental data on a set of benchmark filter designs are provided to show the effectiveness of the proposed exploration strategy in finding close-to-optimal memory configurations.
  • Keywords
    circuit CAD; circuit optimisation; configuration management; digital filters; high level synthesis; integrated circuit design; integrated circuit economics; integrated circuit modelling; integrated memory circuits; performance evaluation; resource allocation; behavioral synthesis; benchmark filter designs; cost evaluation; design automation; high-level synthesis; memory allocation; memory exploration; memory exploration strategy; memory synthesis system coupling; optimal memory configurations; scheduling effects; simultaneous schedule/memory configuration integration; timing-violation checking; Algorithm design and analysis; Clocks; Computer science; Costs; Filters; High level synthesis; Information technology; Libraries; Processor scheduling; Read-write memory;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
  • Print_ISBN
    0-7803-7448-7
  • Type

    conf

  • DOI
    10.1109/ISCAS.2002.1010391
  • Filename
    1010391