Title :
Instruction buffering for nested loops in low power design
Author :
Wu, ChiTa ; Hwang, TingTing
Author_Institution :
Dept. of Comput. Sci., Nat. Tsing Hua Univ., Hsinchu, Taiwan
Abstract :
Loop buffering techniques have been proposed for reducing power consumption. Although such schemes are effective in reducing power, they work for the innermost loop only. In this paper, we propose a stack-based controller which can deal with nested-loops of all styles, and also the if-then-else construct in a loop. Our experiments, using the Wattch power estimator (D. Brooks et al, Int. Symp. Comp. Architecture, pp. 83-94, 2000), show that the power consumption reduction of our technique at fetch and decode stages is up to 40% when compared to that of previously proposed techniques with the innermost loop only.
Keywords :
buffer circuits; buffer storage; circuit CAD; integrated circuit design; integrated circuit modelling; logic CAD; low-power electronics; microprocessor chips; program control structures; Wattch power estimator; fetch/decode stages; if-then-else construct; innermost loop; loop buffering techniques; low power design; nested loop instruction buffering; nested-loops; power consumption reduction; stack-based controller; Buffer storage; Capacitance; Computer science; Displacement control; Energy consumption; Hardware; Iterative decoding;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010393