Design and implementation of structure for debugging cache

With the development of semiconductor technology and the complexity of chip, in some circumstance, the cost of repeated design and manufacture to modify the design mistakes is almost as large as initial design. The cache is an essential part of the processor, in order to ensure the correctness of the design and reduce the cost of debugging cache, the cache should be considered for design-for-debugging. In this paper, the debugging structure is specially designed for the debugging cache, and implemented in Z-CPU. It is convenient to debug the cache by the debugging structure which is simple in logic design, and is smaller in cost of hardware and is applicable to all general-purpose CPU chips.