Low-power multipliers by minimizing switching activities of partial products

Low-power 2´s complement multipliers are developed through minimizing switching activities of partial products using the radix-4 Booth algorithm. Before computation, the input datum with the: smaller effective dynamic range is processed to generate Booth codes, thereby increasing probabilities of partial products being zero. By employing the dynamic-range determination units to control input data paths, the proposed 16×16-bit multipliers based on the Yu, Goldovsky, and Mahant-Shetti´s low-power approaches are individually implemented. To illustrate the proposed multiplier having low-power dissipation, the theoretical analyses of switching activities of partial products are derived. Compared to the power consumed by the conventional multipliers, in applications of the G723.1 speech, ADPCM audio and wavelet-based image coders, the proposed multipliers conserve more than 14%, 30% and 31% of power, respectively. Therefore, the multipliers proposed herein can be widely used for various media processing to achieve low-power consumption at fair hardware costs.