Programmable Active Clock Spine for 100Gb/200Gb Coherent Optical Receiver Chip in 32nm CMOS

Author

Ben-Hamida, Naim ; Kurowski, Christopher ; Gibbins, Robert ; Junxian Weng ; Wong, Ted ; Lindsay, John ; Mah, Harvey ; Aouini, Sadok ; McCarthy, Aongus

Author_Institution

Ciena Corp., Ottawa, ON, Canada

fYear

2014

fDate

19-22 Oct. 2014

Firstpage

1

Lastpage

4

Abstract

This paper describes an active clock distribution network for a 100G/200G coherent optical receiver. The chip has more than 1 billion transistors implemented in 32nm CMOS bulk technology with 11 metal layers. The active clock spines enabled a low-skew, low jitter, and low power clock distribution solution. In addition, a debug-friendly clocking environment provides easy observability, testing, and reconfiguration features; hence, enabling rapid time to market.

Keywords

CMOS integrated circuits; clock distribution networks; low-power electronics; microprocessor chips; optical receivers; timing jitter; CMOS bulk technology; active clock distribution network; coherent optical receiver chip; debug-friendly clocking environment; low jitter clock distribution; low power clock distribution; low-skew clock distribution; metal layers; programmable active clock spine; size 32 nm; storage capacity 100 Gbit; storage capacity 200 Gbit; CMOS integrated circuits; Clocks; Delays; Phase locked loops; Power transmission lines; Synchronization;

fLanguage

English

Publisher

ieee

Conference_Titel

Compound Semiconductor Integrated Circuit Symposium (CSICs), 2014 IEEE

Conference_Location

La Jolla, CA

Type

conf

DOI

10.1109/CSICS.2014.6978574

Filename

6978574