DocumentCode
1804928
Title
A 10-bit 1-GS/s CMOS ADC with FOM = 70 fJ/conversion
Author
Hashemi, Sedigheh ; Razavi, Behzad
Author_Institution
Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA
fYear
2012
fDate
9-12 Sept. 2012
Firstpage
1
Lastpage
4
Abstract
A pipelined ADC incorporates a precharged resistor-ladder DAC in a multi-bit front-end, achieving fast settling and allowing calibration of both dynamic and static gain errors. Using simple differential pairs with a gain of 5 as op amps and realized in 65-nm CMOS technology, the 10-bit ADC consumes 36 mW at a sampling rate of 1 GHz and exhibits an SNDR of 52.7 dB at an input frequency of 490 MHz.
Keywords
CMOS digital integrated circuits; analogue-digital conversion; digital-analogue conversion; operational amplifiers; CMOS ADC; differential pairs; dynamic gain errors; frequency 490 MHz; multibit front-end; op amps; pipelined ADC; power 36 mW; precharged resistor-ladder DAC; size 65 nm; static gain errors; CMOS integrated circuits; Calibration; Capacitors; Clocks; Gain; Noise; Operational amplifiers;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location
San Jose, CA
ISSN
0886-5930
Print_ISBN
978-1-4673-1555-5
Electronic_ISBN
0886-5930
Type
conf
DOI
10.1109/CICC.2012.6330607
Filename
6330607
Link To Document