Performance evaluation of a bufferless N×N synchronous Clos ATM switch with priorities and space preemption

A synchronized bufferless Clos ATM (asynchronous transfer mode) switch with input cell processor queues is considered. The arrival process to each input port of the switch is assumed to be bursty and it is modeled by an interrupted Bernoulli process. Two classes of cells are considered. Service in an input cell processor queue is head-of-line without preemption. In addition, space preemption is used. That is, a high priority cell arriving to a full queue takes the space occupied by the low priority cell with the least waiting time in the queue but not the one in service. Each cell processor queue is modeled as a priority IBP/Geo/1/K+1 queue with space preemption. An exact analysis of the priority queue is presented. The results obtained are then used in an approximation algorithm for the analysis of the ATM switch