Revisiting the Newton-Raphson Iterative Method for Decimal Division

Author

Véstias, Mário P. ; Neto, Horácio C.

Author_Institution

Inst. Super. de Eng. de Lisboa, Polytech. Inst. of Lisbon, Lisbon, Portugal

fYear

2011

fDate

5-7 Sept. 2011

Firstpage

138

Lastpage

143

Abstract

In this paper, we propose an iterative decimal divider. The divider uses the Newton-Raphson iterative method with an initial approximation calculated with a minimax polynomial and is able to use binary multipliers. The proposed circuits were implemented in an FPGA and compared with alternative state-of-the-art solutions. The results indicate that the proposed divider is very competitive in terms of area and latency and better in terms of throughput when compared to decimal dividers based on digit-recurrence algorithms.

Keywords

Newton-Raphson method; approximation theory; field programmable gate arrays; minimax techniques; polynomial approximation; FPGA; Newton-Raphson iterative method; binary multipliers; decimal division; digit-recurrence algorithms; field programmable gate arrays; initial approximation method; iterative decimal divider; minimax polynomial; Adders; Approximation methods; Delay; Iterative methods; Multiplexing; Polynomials; Read only memory; FPGA computing; decimal arithmetic;

fLanguage

English

Publisher

ieee

Conference_Titel

Field Programmable Logic and Applications (FPL), 2011 International Conference on

Conference_Location

Chania

Print_ISBN

978-1-4577-1484-9

Electronic_ISBN

978-0-7695-4529-5

Type

conf

DOI

10.1109/FPL.2011.33

Filename

6044797