DocumentCode :
1805170
Title :
Dual-path architecture of floating-point dot product computation
Author :
Tao, Yao ; Jianfeng, An ; Deyuan, Gao ; Xiaoya, Fan
Author_Institution :
Dept. of Comput. Sci. & Eng., Northwestern Polytech. Univ., Xi´´an, China
Volume :
4
fYear :
2011
fDate :
24-26 Dec. 2011
Firstpage :
2272
Lastpage :
2276
Abstract :
Dot product computation is widely used in many algorithms, such as FFT and DCT. This paper proposes a floating-point dot product architecture based on the multiple-path method. This architecture could perform A×B+C×D as a single operation. The speed of the dual-path architecture implemented in single precision format is faster by 32% and 5.45% than the speed of a network approach using traditional adders and multipliers and the speed of the basic dot product architecture, respectively.
Keywords :
floating point arithmetic; dual-path architecture; floating point dot product architecture; floating point dot product computation; multiple path method; single precision format; Arrays; Hardware design languages; RNA; dot product computation; multple-path method; single operation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Science and Network Technology (ICCSNT), 2011 International Conference on
Conference_Location :
Harbin
Print_ISBN :
978-1-4577-1586-0
Type :
conf
DOI :
10.1109/ICCSNT.2011.6182427
Filename :
6182427
Link To Document :
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