DocumentCode :
1805234
Title :
An Efficient Hardware Matching Engine for Regular Expression with Nested Kleene Operators
Author :
Wakaba, Yoichi ; Inagi, Masato ; Wakabayashi, Shin Ichi ; Nagayama, Shinobu
Author_Institution :
Grad. Sch. of Inf. Sci., Hiroshima City Univ., Hiroshima, Japan
fYear :
2011
fDate :
5-7 Sept. 2011
Firstpage :
157
Lastpage :
161
Abstract :
In this paper, we propose a systolic pattern-independent hardware regular expression matching (REM) engine which handles nested Kleene operators used in virus patterns. Pattern-independent systolic REM engines are suitable to network intrusion detection systems for quick updating of virus pattern. In the proposed engine, we introduce a compact pattern-independent NFA circuit, which can handle any small regular expression patterns, into a systolic REM engine to handle nested Kleene operators. Experimental results show that the extended engine implemented on an FPGA handles nested Kleene operators with efficient circuit size and high performance (2.17 Gbps).
Keywords :
computer networks; computer viruses; control systems; field programmable gate arrays; security of data; telecommunication security; efficient hardware matching engine; nested Kleene operators; network intrusion detection systems; systolic pattern-independent hardware regular expression matching engine; virus patterns; Clocks; Computer architecture; Engines; Hardware; Microprocessors; Pattern matching; Registers; FPGA; NFA; NIDS; regular expression;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Field Programmable Logic and Applications (FPL), 2011 International Conference on
Conference_Location :
Chania
Print_ISBN :
978-1-4577-1484-9
Electronic_ISBN :
978-0-7695-4529-5
Type :
conf
DOI :
10.1109/FPL.2011.36
Filename :
6044800
Link To Document :
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