DocumentCode
1805252
Title
Buffer and wire-size optimization under higher order RLC model for interconnect design
Author
Qi, Chang ; Wang, Gaofeng
Author_Institution
Inst. of Microelectron. & Inf. Technol., Wuhan Univ., Wuhan
Volume
2
fYear
2008
fDate
21-24 April 2008
Firstpage
463
Lastpage
466
Abstract
In this paper, we study the interconnect optimization problem under a higher-order distributed RLC model to optimize not just area and delay, but also waveform and crosstalk for RLC circuit with non-monotone signal response. We propose a new multi-objective genetic algorithm (MOGA) which uses a single objective sorting (SOS) method for constructing the non-dominated set to solve this multi-objective interconnect optimization problem. The MOGA/SOS optimal algorithm provides a smooth trade-off among signal delay, wave form, and routing area. Extensive experimental results show that our algorithm is scalable with problem size. Furthermore, compared to the solution based on an Elmore delay model, our solution reduces the total routing area by up to 30%, the delay to the critical sinks by up to 25%, while further improving crosstalk up to 25.73% on average.
Keywords
RLC circuits; buffer circuits; circuit optimisation; delay circuits; genetic algorithms; integrated circuit interconnections; integrated circuit noise; Elmore delay model; RLC circuits; buffer optimization; crosstalk; higher order RLC model; interconnect design; multi-objective genetic algorithm; routing area; single objective sorting; wire-size optimization; Capacitance; Crosstalk; Delay effects; Design optimization; Genetic algorithms; Inductance; Integrated circuit interconnections; Propagation delay; Sorting; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Microwave and Millimeter Wave Technology, 2008. ICMMT 2008. International Conference on
Conference_Location
Nanjing
Print_ISBN
978-1-4244-1879-4
Electronic_ISBN
978-1-4244-1880-0
Type
conf
DOI
10.1109/ICMMT.2008.4540426
Filename
4540426
Link To Document