Author :
Khakifirooz, A. ; Cheng, K. ; Liu, Q. ; Nagumo, T. ; Loubet, N. ; Reznicek, A. ; Kuss, J. ; Gimbert, J. ; Sreenivasan, R. ; Vinet, M. ; Grenouillet, L. ; Le Tiec, Y. ; Wacquez, R. ; Ren, Z. ; Cai, J. ; Shahrjerdi, D. ; Kulkarni, P. ; Ponoth, S. ; Luning,
Abstract :
We review the basics of the extremely thin SOI (ETSOI) technology and how it addresses the main challenges of the CMOS scaling at the 20-nm technology node and beyond. The possibility of VT tuning with backbias, while keeping the channel undoped, opens up new opportunities that are unique to ETSOI. The main device characteristics with regard to low-power and high-performance logic, SRAM, analog and passive devices, and embedded memory are reviewed.
Keywords :
CMOS integrated circuits; silicon-on-insulator; system-on-chip; CMOS scaling; ETSOI technology; SRAM; VT tuning; analog devices; backbias; embedded memory; extremely thin SOI; low-power high-performance logic; main device characteristics; passive devices; system-on-chip applications; CMOS integrated circuits; Doping; FinFETs; Junctions; Logic gates; Random access memory;
