Novel macromodeling for on-chip RC/RLC interconnects

The improved T and improved Π models are proposed for on-chip interconnect macromodeling. Using global approximations, simple approximation frames are derived and applied to modeling of on-chip distributed RC/RLC interconnects. The applications lead to equivalent circuits, which are represented by the improved T and improved Π models. The new models for distributed RC/RLC interconnects are independent of CMOS gates, and therefore can be directly incorporated into SPICE frames. Numerical experiments show that for current feature sizes, the improved T and improved Π modeling methods can be used to accurately evaluate onchip interconnect effects, while the computational costs are comparable to the original T and Π modeling. The presented macromodeling approaches are useful for quick simulation and layout optimization.