Title :
An energy efficient 32nm 20 MB L3 cache for Intel® Xeon® processor E5 family
Author :
Huang, Min ; Mehalel, Moty ; Arvapalli, Ramesh ; He, Songnian
Abstract :
A 20-way set associative 20MB energy efficient L3 this paper. The design uses 0.2119um2 cell and is manufactured in the 32nm second generation of high-K dielectric metal gate process with 9-copper layers. The power efficiency was achieved by employing advanced power saving schemes and effective Vccmin design techniques. The proposed L3 cache topology seamlessly supports a high density modular and energy efficient designs.
Keywords :
cache storage; high-k dielectric thin films; Intel Xeon processor E5 family; L3 cache topology; advanced power saving schemes; copper layers; effective voltage design techniques; energy efficient L3 cache; high-k dielectric metal gate process; size 32 nm; storage capacity 20 Mbit; Arrays; Energy efficiency; Random access memory; Switching circuits; Threshold voltage; Transistors;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4673-1555-5
Electronic_ISBN :
0886-5930
DOI :
10.1109/CICC.2012.6330624
