DocumentCode
1805437
Title
Design Methods for Multiple-Valued Input Address Generators
Author
Sasao, Tsutomu
Author_Institution
Kyushu Institute of Technology, Japan
fYear
2006
fDate
17-20 May 2006
Firstpage
1
Lastpage
1
Abstract
A multiple-valued input address generator produces a unique address given a multiple-valued input data vector. This paper presents methods to realize multiple-valued input address generators by multi-level networks of p-input q-output memories. It shows a method to simplify the address generators using an auxiliary memory.
Keywords
Circuit testing; Computer science; Databases; Design methodology; Dictionaries; Fuzzy logic; Internet; Logic design; Logic testing; Programmable logic arrays;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 2006. ISMVL 2006. 36th International Symposium on
ISSN
0195-623X
Print_ISBN
0-7695-2532-6
Type
conf
DOI
10.1109/ISMVL.2006.17
Filename
1623953
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