DocumentCode :
1805536
Title :
A new pipelined adaptive DFE architecture with improved convergence rate
Author :
Yang, Meng-Da ; Wu, An-Yeu Andy
Author_Institution :
Graduate Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume :
4
fYear :
2002
fDate :
2002
Abstract :
Among existing works of high-speed pipelined adaptive decision feedback equalizer (ADFE), the pipelined ADFE using relaxed look-ahead technique results in a substantial hardware saving over the parallel processing or look-ahead approaches. However, it suffers from the SNR degradation and slow convergence rate. In this paper, a new pipelining ADFE architecture is developed. By employing the post-processing filter (PF) to cancel the most significant post-cursor inter-symbol interference (ISI) terms, the proposed ADFE architecture can help to improve the convergence rate of ADFE compared with the relaxed look-ahead ADFE architecture while at the same hardware cost. It provides an alternative approach for the design of high-seed pipelining ADFE with large speedup factor.
Keywords :
adaptive equalisers; decision feedback equalisers; intersymbol interference; pipeline processing; SNR degradation; convergence rate; decision feedback equalizer; hardware saving; high-seed pipelining; pipelined adaptive DFE architecture; post-cursor inter-symbol interference; post-processing filter; relaxed look-ahead technique; speedup factor; Convergence; Costs; Decision feedback equalizers; Degradation; Filters; Hardware; Interference cancellation; Intersymbol interference; Parallel processing; Pipeline processing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
Type :
conf
DOI :
10.1109/ISCAS.2002.1010427
Filename :
1010427
Link To Document :
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