Title :
SpiNNaker: A multi-core System-on-Chip for massively-parallel neural net simulation
Author :
Painkras, Eustace ; Plana, Luis A. ; Garside, Jim ; Temple, Steve ; Davidson, Simon ; Pepper, Jeffrey ; Clark, David ; Patterson, Cameron ; Furber, Steve
Author_Institution :
Univ. of Manchester, Manchester, UK
Abstract :
The modelling of large systems of spiking neurons is computationally very demanding in terms of processing power and communication. SpiNNaker is a massively-parallel computer system designed to model up to a billion spiking neurons in real time. The basic block of the machine is the SpiNNaker multicore System-on-Chip, a Globally Asynchronous Locally Synchronous (GALS) system with 18 ARM968 processor nodes residing in synchronous islands, surrounded by a light-weight, packet-switched asynchronous communications infrastructure. The MPSoC contains 100 million transistors in a 102 mm2 die, provides a peak performance of 3.96 GIPS and has a power consumption of 1W at 1.2V when all processor cores operate at nominal frequency. SpiNNaker chips were delivered in May 2011, were fully operational, and met power and performance requirements.
Keywords :
digital simulation; microprocessor chips; multiprocessing systems; neural nets; parallel processing; system-on-chip; ARM968 processor nodes; GALS system; MPSoC; SpiNNaker; globally asynchronous locally synchronous system; massively-parallel computer system; massively-parallel neural net simulation; multicore system-on-chip; packet-switched asynchronous communications infrastructure; power 1 W; spiking neurons; synchronous islands; voltage 1.2 V; Brain modeling; Clocks; Computational modeling; Decoding; Neurons; SDRAM; System-on-a-chip;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4673-1555-5
Electronic_ISBN :
0886-5930
DOI :
10.1109/CICC.2012.6330636
