DocumentCode
1805750
Title
The new architecture of radix-4 Chinese abacus adder
Author
Yi, Shu-Chung ; Lee, Kun-Tse ; Chen, Jin-Jia ; Lin, Chien-Hung ; Wang, Chuen-Ching ; Hsieh, Chin-Fa ; Lu, Chih-Yung
Author_Institution
National Changhua University of Education, Changhua, Taiwan
fYear
2006
fDate
17-20 May 2006
Firstpage
12
Lastpage
12
Abstract
In this paper, we present a new architecture of Chinese abacus adder. As high radix of adder may reduce the number of carry propagation, the proposed Chinese abacus adder may achieve high-speed operation. The simulation results of our work are compared with CLA (Carry Look-ahead) adder. The delay of the 8-bit abacus adders are 22%, 17%, and 14% less than those of CLA adders for 0.35µm, 0.25µm, and 0.18µm technologies, respectively. The power consumption of the abacus adders are 30%, 34%, and 60% less than those of CLA adders for 0.35µm, 0.25µm, and 0.18µm technologies, respectively. The use of Chinese abacus approach results a competitive technique with respect to conventional fast adder.
Keywords
Added delay; Adders; Circuits; Design methodology; Digital arithmetic; Educational technology; Energy consumption; Equations; Logic;
fLanguage
English
Publisher
ieee
Conference_Titel
Multiple-Valued Logic, 2006. ISMVL 2006. 36th International Symposium on
ISSN
0195-623X
Print_ISBN
0-7695-2532-6
Type
conf
DOI
10.1109/ISMVL.2006.41
Filename
1623964
Link To Document