A 4-bit 12GS/s data acquisition System-on-Chip including a flash ADC and 4-channel DeMUX in 130nm CMOS

This paper presents design and implementation of a 12GS/s fully differential data acquisition (DAQ) System-on-Chip (SoC) in a standard 130nm CMOS process. The 12 GS/s DAQ system includes a 4-bit flash ADC and 4 channels of 1:32 DeMUX with on-chip custom registers. At 12GS/s sampling rate, the DAQ SoC achieves an SNDR of 19.2 dB for 2.9GHz input and 24.2 dB for low frequency inputs. The flash ADC and each DeMUX channel consume 200- and 260- mA from 1.3V supply, respectively. The active area of flash ADC and each DeMUX channel is 0.85- and 0.70-mm², respectively. The DAQ SoC does not employ time-interleaving and calibration techniques. Moreover, no BW- or speed-enhancing inductors have been used in the design. The circuit achieves the highest sampling rate in a standard 130nm CMOS technology.