DocumentCode :
1805935
Title :
A High-Density Ternary Content-Addressable Memory Using Single-Electron Transistors
Author :
Degawa, Katsuhiko ; Aoki, Takafumi ; Higuchi, Tatsuo ; Inokawa, Hiroshi ; Nishiguchi, Katsuhiko ; Takahashi, Yasuo
Author_Institution :
Tohoku University, Sendai 980-8579, Japan
fYear :
2006
fDate :
17-20 May 2006
Firstpage :
19
Lastpage :
19
Abstract :
This paper presents a circuit design of a Ternary Content-Addressable Memory (TCAM) using Single- Electron Transistors (SETs). The proposed TCAM cell employs a SET-based ternary memory and a dual-gate SET for ternary data matching. The multi-level functionality of SET is fully utilized to reduce circuit complexity. Basic matching operation of the TCAM cell is verified using a multi-gate SET and a MOSFET fabricated on the same Silicon-On-Insulator (SOI) wafer by Pattern-Dependent OXidation (PADOX) process.
Keywords :
CADCAM; CMOS logic circuits; CMOS technology; Circuit synthesis; Computer aided manufacturing; Integrated circuit technology; Multilevel systems; Pattern matching; Silicon on insulator technology; Single electron transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multiple-Valued Logic, 2006. ISMVL 2006. 36th International Symposium on
ISSN :
0195-623X
Print_ISBN :
0-7695-2532-6
Type :
conf
DOI :
10.1109/ISMVL.2006.6
Filename :
1623971
Link To Document :
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