A 5GHz 0.18-μm CMOS technology PLL with a symmetry PFD

A fast-locking low-jitter phase-locked loop (PLL) with a simple phase-frequency detector has been proposed. The phase-frequency detector is composed of only two XOR gates. It can achieve performances of both low jitter and short locking time simultaneously. The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45 degrees. The PLL is fabricated in a 0.18-mum CMOS technology. Measured phase noise of the PLL output at 500 kHz offset from the 5 GHz center frequency is -102.6 dBc/Hz. The circuit exhibits a capture range of 280 MHz and a low rms jitter of 2.0 6 s. The power dissipation excluding the output buffers is only 21.6 mW at a 1.8-V supply.