Title :
A fully integrated 3.3-V, 325-MHz, ±95-ps jitter CMOS PLL
Author :
Sulaiman, Mohd S. ; Dryburgh, Thomas ; Elmasry, M.I.
Author_Institution :
Fac. of Eng., Multimedia Univ., Cyberjaya, Malaysia
Abstract :
A programmable Phase-Locked Loop architecture designed as an embedded feature in an FPGA is presented. The PLL was designed based on advanced low-power high-performance circuit design techniques, with low-output jitter, low power, and able to tolerate variations in the fabrication process. The PLL is able to generate clock signals from 61 MHz-325 MHz from a low-frequency system clock, with a maximum output jitter of ±95 ps.
Keywords :
CMOS digital integrated circuits; clocks; field programmable gate arrays; phase locked loops; timing jitter; 100 ps; 3.3 V; 61 to 325 MHz; 90 ps; CMOS PLL; FPGA; VLSI; lock signal generation; low power high-performance circuit design techniques; on-chip clock generation; output jitter; programmable phase locked loop architecture design; Charge pumps; Circuits; Decoding; Frequency response; Jitter; Low pass filters; Phase detection; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators;
Conference_Titel :
Semiconductor Electronics, 2002. Proceedings. ICSE 2002. IEEE International Conference on
Print_ISBN :
0-7803-7578-5
DOI :
10.1109/SMELEC.2002.1217777
