Title :
A 2.4-GHz, 3.74-mW CMOS PLL-based frequency synthesizer
Author :
Sulaiman, Mohd S.
Author_Institution :
Fac. of Eng., Multimedia Univ., Selangor, Malaysia
Abstract :
A low-power high-performance PLL-based frequency synthesizer architecture is presented. The PLL was designed based on advanced low-power approaches such as clock gating, variable charge-pump current, and single-phase clocking techniques. The 880 MHz-2.4 GHz PLL was designed using a CMOS 0.18-μm technology. Post parasitics-extracted layout results verify that the average power dissipation of the PLL is 3.74 mW (at 2.4 GHz, 1.8 V).
Keywords :
frequency synthesizers; phase locked loops; 0.18 micron; 1.8 V; 3.74 mW; 880 MHz to 2.4 GHz; CMOS PLL-based frequency synthesizer; clock gating; low power high-performance PLL based frequency synthesizer architecture; power dissipation; single phase clocking; variable charge-pump current; Charge pumps; Circuit noise; Filters; Frequency synthesizers; Noise figure; Phase detection; Phase frequency detector; Phase locked loops; Phase noise; Voltage;
Conference_Titel :
Semiconductor Electronics, 2002. Proceedings. ICSE 2002. IEEE International Conference on
Print_ISBN :
0-7803-7578-5
DOI :
10.1109/SMELEC.2002.1217778
