Title :
Design rewiring for power minimization [logic design]
Author :
Amiri, Mandana ; Veneris, Andrcas ; Ting, Ivor
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
A new ATPG-based approach to multi-level combinational logic circuit power optimization is presented. This method borrows from existing simulation-based design error diagnosis and correction techniques. At every step of the optimization procedure, a design error is introduced by removing logic with high switching activity and it is corrected by modifying the design in a less critical area. The experiments presented here indicate the added flexibility and potential of this approach.
Keywords :
automatic test pattern generation; circuit layout CAD; circuit optimisation; combinational circuits; error correction; integrated circuit layout; integrated logic circuits; iterative methods; logic CAD; logic testing; low-power electronics; multivalued logic circuits; ATPG-based approach; design error; design rewiring; diagnosis techniques; logic circuit power optimization; low power design; multi-level combinational logic circuit; power minimization; Automatic test pattern generation; Circuit simulation; Constraint optimization; Design methodology; Design optimization; Error correction; Logic circuits; Logic design; Redundancy; Wire;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010451
