Title :
A 240mW 2.1GS/s 12b pipeline ADC using MDAC equalization
Author :
Wu, Jiangfeng ; Chen, Chun-Ying ; Li, Tianwei ; Liu, Wenbo ; He, Lin ; Tsai, Shauhyuarn Sean ; Chen, Binning ; Huang, Chun-Sheng ; Hung, Juo-Jung ; Shih, Wei-Ta ; Hung, Hing ; Jaffe, Steven ; Tan, Loke ; Vu, Hung
Author_Institution :
Broadcom Corp., Irvine, CA, USA
Abstract :
This paper introduces MDAC equalization, a digital correction technique for pipeline ADCs that corrects MDAC gain and settling errors using successive digital FIR filters operating on sub-ADC output samples. This technique reduces the required MDAC residue amplifier (RA) bandwidth relative to the sampling frequency, thereby reducing ADC power. MDAC equalization is demonstrated in a 240mW 2.1GS/s 12b ping-pong pipeline ADC in 40nm CMOS where MDAC RA power is reduced from 175mW to 53mW by 70%.
Keywords :
CMOS analogue integrated circuits; FIR filters; analogue-digital conversion; digital-analogue conversion; equalisers; power amplifiers; ADC power; CMOS; MDAC RA power; MDAC equalization; MDAC gain; RA bandwidth; bit rate 2.1 Gbit/s; digital FIR filter; digital correction technique; ping-pong pipeline ADC; power 175 mW; power 240 mW; power 53 mW; residue amplifier; sampling frequency; size 40 nm; subADC output; Accuracy; Bandwidth; CMOS integrated circuits; Calibration; Equalizers; Finite impulse response filter; Pipelines;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4673-1555-5
Electronic_ISBN :
0886-5930
DOI :
10.1109/CICC.2012.6330654
