JPEG-2000 on an advanced architecture, multiple execution unit DSP

This paper presents an analysis of the factors to be considered in the system design of JPEG-2000 on an advanced architecture digital signal processor (DSP) with a focus on achieving parallelism of the multiple execution units of the DSP in a SIMD processing model. The results of implementation of a feature rich JPEG-2000 codec developed on Motorola Star*Core™ have been presented, the focus being on the decoding performance figures. The results will be useful in understanding the effect of the coding options of JPEG-2000 and, in the design of JPEG-2000 based embedded systems and hardware solutions or in a combined hardware-firmware solution. To our knowledge, this is the first analysis of a DSP based implementation of JPEG-2000 reported in literature.