DocumentCode
1806293
Title
A hardware accelerator for video segmentation using programmable morphology PE array
Author
Chien, Shao-Yi ; Huang, Yu-Wen ; Chen, Liang-Gee
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
4
fYear
2002
fDate
2002
Abstract
Video segmentation is a key operation for MPEG-4 and MPEG-7. It is a computationally intensive task and cannot be afforded by general microprocessors. In this paper, we propose a hardware accelerator for video segmentation. Since most of the core operations of video segmentation algorithms can be mapped to morphological operations, the core of this accelerator is a programmable morphology PE array. With the programmable ability of each PE and the interconnection between them, this accelerator can achieve both high throughput and high flexibility. Simulation shows the proposed hardware accelerator can speed up the most important video segmentation algorithms 20 times to achieve realtime performance and has high programmability with a little hardware cost overhead.
Keywords
image segmentation; mathematical morphology; video signal processing; MPEG-4; MPEG-7; cost overhead; flexibility; hardware accelerator; morphological operations; programmable morphology PE array; throughput; video segmentation; Algorithm design and analysis; Change detection algorithms; Hardware; Image edge detection; MPEG 4 Standard; Morphological operations; Morphology; Optical filters; Signal processing algorithms; Videoconference;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN
0-7803-7448-7
Type
conf
DOI
10.1109/ISCAS.2002.1010460
Filename
1010460
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