DocumentCode
1806313
Title
Power Efficient Large Matrices Multiplication by Load Scheduling on Multi-core and GPU Platform with CUDA
Author
Ren, DaQi ; Suda, Reiji
Author_Institution
Dept. of Comput. Sci., Univ. of Tokyo, Tokyo, Japan
Volume
1
fYear
2009
fDate
29-31 Aug. 2009
Firstpage
424
Lastpage
429
Abstract
Power efficiency is one of the most important issues in high performance computing (HPC) interrelated to both software and hardware. Power dissipation of a program lies on algorithm design and power features of the computer components on which the program runs. In this work, we measure and model the power consumption of large matrices multiplication on multi-core CPU and GPU platform. By incorporating major physical power constrains of hardware components with the analysis of program execution behaviors, we approach to save the overall power consumption by using multithreading CPU to control two GPU devices computing in parallel synchronously. By implementing above method on real system, we show that it can save 22% of energy and speedup the kernel execution time by 71%, compare with solving the same large matrices multiplication using single CPU and GPU combination.
Keywords
computer graphic equipment; matrix multiplication; multi-threading; parallel processing; power aware computing; resource allocation; CUDA; GPU platform; load scheduling; matrices multiplication; multicore CPU; multithreading CPU; power efficiency; Algorithm design and analysis; Concurrent computing; Energy consumption; Hardware; High performance computing; Multithreading; Power dissipation; Power measurement; Processor scheduling; Software performance;
fLanguage
English
Publisher
ieee
Conference_Titel
Computational Science and Engineering, 2009. CSE '09. International Conference on
Conference_Location
Vancouver, BC
Print_ISBN
978-1-4244-5334-4
Electronic_ISBN
978-0-7695-3823-5
Type
conf
DOI
10.1109/CSE.2009.488
Filename
5283370
Link To Document