Title :
A low-power highly multiplexed parallel PRBS generator
Author :
Chen, Ming-Shuan ; Yang, Chih-Kong Ken
Author_Institution :
Univ. of California, Los Angeles, CA, USA
Abstract :
For high data rates, pseudo-random bit sequence (PRBS) patterns must be generated in parallel and then multiplexed. This paper introduces a design that reduces the number of XORs and DFFs to lower power dissipation and area. The maximum fan-out can be further constrained to improve gate delay and hence improve the output data rate. The procedure for applying the design to arbitrary PRBS lengths is provided and the design is suitable for standard-cell design flow. The design achieves 1.7-Gb/s data rate with 64-way multiplexing to support an output bandwidth of >;100 Gb/s. The design is implemented in an 65-nm technology using 0.007 mm2 area and dissipating 0.16 mW of power.
Keywords :
logic circuits; low-power electronics; multiplexing; random number generation; DFF; XOR; bit rate 1.7 Gbit/s; gate delay; low-power highly multiplexed parallel PRBS generator; lower power dissipation; multiplexing; power 0.16 mW; pseudo-random bit sequence patterns; size 65 nm; BiCMOS integrated circuits; CMOS integrated circuits; CMOS technology; Generators; Multiplexing; Silicon germanium; Transceivers;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4673-1555-5
Electronic_ISBN :
0886-5930
DOI :
10.1109/CICC.2012.6330664
