6T SRAM and 3T DRAM data retention and remanence characterization in 65nm bulk CMOS

While SRAM and DRAM are often assumed to have very small data retention times (bits are lost immediately at power-down) and no data remanence (stored bits leave no traces even after a prolonged storage period), under some conditions these assumptions do not hold. Both retention and remanence have been exploited by malicious attackers to compromise system data and encryption keys in secure systems. To precisely measure retention and remanence in SRAM and DRAM, we implemented specially instrumented 6T SRAM and 3T DRAM test structures in 65nm bulk CMOS and tested them from -40°C to 85°C and under accelerated aging conditions. Results show that the 50% retention time (i.e., half the bits retained data) is 44 ms for the 6T SRAM and 3.8 ms for the 3T DRAM at -40°C. Further, the data remanence effects were exploited to predict stored bits with over 82% accuracy for 22% of a 4kb SRAM array.