Design and analysis of low timing-skew clock generation for time-interleaved sampled-data systems

Author

Seng-Pan, U. ; Martins, R.P. ; Franca, J.E.

Author_Institution

Fac. of Sci. & Technol., Univ. of Macau, China

Volume

4

fYear

2002

fDate

2002

Abstract

This paper analyzes the output phase-skew effects related to practical sample-and-hold embedding in high-speed, time-interleaved sampled-data systems. Closed-formed expressions are presented and verified by numerical computer simulations. Special design techniques and layout issues for reducing both the random process and systematic mismatches are presented through a real application of a low phase-skew clock generation circuit that is used for a very high-frequency SC multirate filter with 320 MHz output sampling rate. Measurement results (skew noise tones <-72 dBc) further verify the proposed techniques.

Keywords

VHF filters; circuit simulation; clocks; integrated circuit layout; sampled data filters; signal generators; signal sampling; switched capacitor filters; timing; 56 to 58 MHz; closed-formed expressions; design techniques; layout issues; low phase-skew clock generation circuit; low timing-skew clock generation; numerical computer simulations; output phase-skew effects; output sampling rate; random process reduction; sample-and-hold embedding; skew noise tones; systematic mismatch reduction; time-interleaved sampled-data systems; very high frequency SC multirate filter; Clocks; Equations; Filters; Frequency; MATLAB; Mathematical model; Phase noise; Sampling methods; Signal sampling; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010486

Filename

1010486