FPGA Interconnect Architecture Exploration Based on a Statistical Model

This paper presents a novel statistical model to help exploring the FPGA interconnect architecture design space efficiently. A series of parameters featuring the GRM-based (General Routing Matrix) interconnect architecture are defined. By analyzing these parameters such as routing segments type, channel width and drive relation, our model is able to calculate the average hops indicator which is approved in experiments to be a good estimation of the timing performance of architectures. With our model, we evaluate hundreds of architectures and figure out the formula expressing the possible trade-offs between performance and area. We select several representatives and conclude that routing segment is still a powerful tool in design trade-offs.