Test processor chip design with complete simulation result including reseeding technique

Infected circuits are becoming more complex with increased density. Consequently, IC testing is also becoming more complex according to the complexity and density of ICs. This paper presents the simulation result of a test processor chip design which includes a complete reseeding technique and an effective seed selection. Using linear feed back shift register (LFSR) based test pattern generator (TPG) different test vectors have been applied for efficient result by using 24-bit test length. An improved reseeding technique has been applied for reduced test length and time. RAM and signature analyzer have been used for storage and comparison purpose.