Modeling the response of Bang-Bang digital PLLs to phase error perturbations

Bang-Bang phase locked loops (BB-PLLs) offer a low power implementation of digital PLLs. However, the response of BB-PLLs, unlike linear PLLs, depends on the magnitude of the phase error, and thus, exhibits hard nonlinearity. This paper presents a generic modeling methodology for digital BB-PLLs in the locked state using simple time domain analysis. The proposed model predicts the response of BB-PLL to a given phase error magnitude in terms of stability (maintaining lock), and settling time (relock time). The model further aids the design process by providing insight for the system response in terms of the loop parameters. An example BB-PLL system is implemented in 32nm technology, and the proposed model is applied. Verified by analog-mixed signal (AMS) simulations, the model was successful in predicting the system response, and indicating stability and settling time of the system for a given phase error magnitude.