Synthesizing Tiled Matrix Decomposition on FPGAs

Hardware accelerators such as FPGAs and GPUs in heterogeneous systems are being increasingly important for many applications. For high performance computing, the flexibility and efficiency of FPGA makes it an attractive alternative to other approaches. However, for applications that have to decompose large matrices, not many scalable solutions can be found on FPGAs. In this paper, we propose a scalable QR matrix decomposer on FPGAs based on the latest advances in tiled matrix decomposition algorithms for high performance linear algebra. The proposed design can decompose a matrix of size limited only by off-chip memory and has the potential to achieve high performance.