Title :
RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers for SoC applications
Author :
Neve, Cesar Roda ; Ben Alia, K. ; Malaquin, C. ; Allibert, F. ; Desbonnets, E. ; Bertrand, Isabelle ; Van Den Daele, W. ; Raskin, J.
Author_Institution :
Inst. of Inf. & Commun. Technol., Electron. & Appl. Math. (ICTEAM), Univ. catholique de Louvain (UCL), Louvain-la-Neuve, Belgium
Abstract :
We present for the first time the RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers. These wafers are fully compatible with the thermal budget of CMOS process. The investigated SOI wafers with a fixed BOX of 400 nm-thick show effective resistivity values higher than 4 kΩ-cm and harmonic distortion levels lower than -81 dBm for a 900 MHz input signal with +15 dBm, i.e. more than 95 dBc. Our investigations confirm the capability of trap-rich HR-SOI wafer for the integration of RF systems in Si.
Keywords :
CMOS integrated circuits; elemental semiconductors; harmonic distortion; integrated circuit modelling; silicon; silicon-on-insulator; system-on-chip; CMOS process; SoC; fixed BOX; frequency 900 MHz; harmonic distortion; high resistivity silicon-on-insulator; size 200 nm; size 400 nm; system-on-chip; thermal budget; trap-rich HR-SOI wafers; Conductivity; Coplanar waveguides; Harmonic distortion; Radio frequency; Silicon; Silicon-on-insulator; Substrates; HR SOI; RF integration; SoC; TR SOI; substrate non-linearity; trap-rich HR SOI; trap-rich layer;
Conference_Titel :
Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 2013 IEEE 13th Topical Meeting on
Conference_Location :
Austin, TX
Print_ISBN :
978-1-4673-1552-4
Electronic_ISBN :
978-1-4673-1551-7
DOI :
10.1109/SiRF.2013.6489417
