Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits

Abnormal increase of the crosstalk noise in the sub-threshold logic circuits is found for the first time. When the threshold voltages (V_TH) of nMOS and pMOS are imbalanced and the on-resistance of the aggressor driver is much lower than that of the victim driver, the large crosstalk noise is observed, because the on-resistance has an exponential dependence on V_TH in the sub-threshold circuits. In this paper, the large crosstalk noise due to the imbalanced V_TH is measured. A new crosstalk noise model is also proposed and verified with SPICE simulations. In a crosstalk noise test chip with 1.5-mm wire in a 40-nm CMOS at the power supply voltage (V_DD) of 0.3V, the measured noise amplitude increases from 32% of V_DD to 71% of V_DD, when the imbalanced V_TH is realized by tuning a body bias in pMOS. In the worst case fast-nMOS/slow-pMOS corner simulations, the noise amplitude increases from 47% of V_DD to 68% of V_DD, when V_DD is reduced from 1.1V to 0.3V, which is explained by the proposed model.