DocumentCode
1807403
Title
A continuous-time ΔΣ modulator with 87 dB dynamic range in a 2MHz signal bandwidth using a Switched-Capacitor Return-to-Zero DAC
Author
Nandi, Timir ; Boominathan, Karthikeya ; Pavan, Shanthi
Author_Institution
Indian Inst. of Technol. Madras, Chennai, India
fYear
2012
fDate
9-12 Sept. 2012
Firstpage
1
Lastpage
4
Abstract
We introduce the Switched-Capacitor Return-to-Zero (SCRZ) DAC, which combines the low clock jitter sensitivity of a Switched-Capacitor DAC with the low distortion of a Return-to-Zero DAC. A single-bit continuous-time ΔΣ modulator that uses the SCRZ technique and opamp-assistance to improve DAC linearity and reduce jitter sensitivity achieves 87.1/84.5/82.3 dB DR/SNR/SNDR in a 2 MHz bandwidth. Operating at a sampling rate of 256 MHz in a 0.18 μm CMOS process, the CTDSM dissipates 16.5 mW from a 1.8 V supply.
Keywords
CMOS integrated circuits; continuous time systems; delta-sigma modulation; jitter; switched capacitor networks; CMOS process; bandwidth 2 MHz; frequency 256 MHz; low clock jitter sensitivity; opamp-assistance; power 16.5 mW; single-bit continuous-time ΔΣ modulator; size 0.18 mum; switched-capacitor return-to-zero DAC; voltage 1.8 V; Capacitors; Clocks; Jitter; Linearity; Modulation; Noise; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location
San Jose, CA
ISSN
0886-5930
Print_ISBN
978-1-4673-1555-5
Electronic_ISBN
0886-5930
Type
conf
DOI
10.1109/CICC.2012.6330692
Filename
6330692
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