DocumentCode
1807500
Title
A 0.015mm2 63fJ/conversion-step 10-bit 220MS/s SAR ADC with 1.5b/step redundancy and digital metastability correction
Author
Vitek, R. ; Gordon, E. ; Maerkovich, S. ; Beidas, A.
fYear
2012
fDate
9-12 Sept. 2012
Firstpage
1
Lastpage
4
Abstract
A low power and very low area 10-bit 220MS/s SAR ADC is presented. The ADC employs a redundancy scheme that relaxes the DAC settling requirement and enables high sample rates, as well as a digital metastability identification and correction algorithm that exploits the redundancy as an error-correction code. The proposed ADC was implemented in CMOS 65nm, and takes up only 0.015mm2. At 220MS/s it consumes 4.3mW and achieves 51.7dB SNDR for a full scale sinusoidal input. For OFDM-like signals (wide-band 13dB Peak-to-RMS) the equivalent ENOB is 9.1 bit at 220MS/s. The figure-of-merit (FOM) is 63fJ/(conversion-step) at 220MS/s and 43fJ/conv-step at 160Ms/s.
Keywords
OFDM modulation; analogue-digital conversion; error correction codes; CMOS; DAC settling requirement; OFDM-like signal; SAR ADC; SNDR; digital metastability correction; digital metastability identification; error-correction code; figure-of-merit; power 4.3 mW; redundancy scheme; word length 10 bit; CMOS integrated circuits; Capacitors; OFDM; Phase locked loops; Redundancy; Switches; Wireless communication;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location
San Jose, CA
ISSN
0886-5930
Print_ISBN
978-1-4673-1555-5
Electronic_ISBN
0886-5930
Type
conf
DOI
10.1109/CICC.2012.6330696
Filename
6330696
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