Title :
A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS
Author :
Shin, Soon-Kyun ; Rudell, Jacques C. ; Daly, Denis C. ; Muñoz, Carlos E. ; Chang, Dong-Young ; Gulati, Kush ; Lee, Hae-Seung ; Straayer, Matthew Z.
Author_Institution :
Dept. of Electr. Eng., Univ. of Washington, Seattle, WA, USA
Abstract :
A 12-bit 200MS/s zero-crossing based pipeline ADC is presented. A coarse phase followed by a level-shifted fine phase is employed for higher accuracy. To enable high frequency operation, sub-ADC flash comparators are strobed immediately after the coarse phase. The ADC occupies 0.276mm2 in 55nm CMOS and dissipates 28.5mW. 62.5dB SNDR and 78.6dBc SFDR with a 99.6MHz input signal at 200MS/s are achieved for a FOM of 131fJ/step. The reference buffer, bias circuitry, and digital error correction circuits are all implemented on chip.
Keywords :
CMOS integrated circuits; analogue-digital conversion; buffer circuits; comparators (circuits); CMOS; FOM; SFDR; SNDR; bias circuitry; coarse phase; digital error correction circuits; frequency 99.6 MHz; frequency scalable zero-crossing based pipelined ADC; high frequency operation; level-shifted fine phase; power 28.5 mW; reference buffer; size 55 nm; subADC flash comparators; word length 12 bit; CMOS integrated circuits; Capacitors; Charge transfer; Detectors; Frequency measurement; Linearity; Power demand;
Conference_Titel :
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location :
San Jose, CA
Print_ISBN :
978-1-4673-1555-5
Electronic_ISBN :
0886-5930
DOI :
10.1109/CICC.2012.6330697
