Title :
Full current-mode techniques for high-speed CMOS SRAMs
Author :
Wang, S.M. ; Wu, C.-Y.
Author_Institution :
Nat. Chiao Tung Univ., Hsinchu, Taiwan
Abstract :
This paper describes an experimental 32 K×8 CMOS SRAM with a 9 ns access time at a supply voltage of 3 V using a 0.35 μm 1P2M CMOS logic technology. Based on the full current-mode techniques for read/write operation, the sensing speed and write pulse width are insensitive to the bit-line capacitance. Due to these techniques, the voltage swing at the bit-line and data-line can be kept quite small all the time. The active current is 28 mA at 100 MHz under typical conditions.
Keywords :
CMOS memory circuits; SRAM chips; current-mode circuits; high-speed integrated circuits; low-power electronics; 0.35 micron; 100 MHz; 1P2M CMOS logic technology; 256 K; 28 mA; 3 V; 9 ns; bit-line capacitance; current-mode sense amplifier; current-mode write driver; full current-mode techniques; high-speed CMOS SRAMs; low power SRAM; read/write operation; sensing speed; static RAMs; write pulse width; CMOS technology; Capacitance; Circuits; Delay; Energy consumption; Flip-flops; Latches; Power dissipation; Random access memory; Voltage;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010522
