Title :
Variation tolerant digitally assisted high-speed IO PHY
Author :
Roytman, Eduard ; Nagarajan, Mali ; Shah, Rahul ; Ma, Xin ; Bedard, Ronald ; Munshi, Kambiz ; Iknaian, Russell ; Cai, Fengxiang ; Xu, Jian ; Devi, Gayathri Sridharan ; Vempada, Pradeep
Author_Institution :
Intel Corp., Hudson, MA, USA
Abstract :
Technology scaling leads to reduction of supply voltage and increase in random device variability and thus creates new challenges for analog design. A complete overhaul of the design approach at system architecture and circuit topology levels is necessary to keep the link robust and tolerant to low supply voltage and random variability challenges. This paper presents key analog circuit architecture techniques employed to implement 6.4GT/s per lane, 14mW/Gbps analog front end high-speed IO interfaces on Poulson - a 32nm next generation Intel Itanium microprocessor [1].
Keywords :
high-speed integrated circuits; integrated circuit design; integrated circuit manufacture; integrated circuit testing; low-power electronics; microprocessor chips; network topology; peripheral interfaces; random processes; Poulson; analog design; analog front end high-speed IO interfaces; circuit topology levels; key analog circuit architecture techniques; low supply voltage; next generation Intel Itanium microprocessor; random device variability; random variability challenges; supply voltage reduction; system architecture; technology scaling; variation tolerant digitally assisted high-speed IO PHY; Clocks; Feedback loop; Jitter; Microprocessors; Receivers; Resistors; Transmitters;
Conference_Titel :
ESSCIRC (ESSCIRC), 2011 Proceedings of the
Conference_Location :
Helsinki
Print_ISBN :
978-1-4577-0703-2
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2011.6044890
