Low-power 2P2N SRAM with column hidden refresh

A column hidden refresh technique is proposed for the 2P2N SRAM design. All of the storage nodes of the 2P2N cells in the same column are refreshed simultaneously. The dissipated power of the column hidden refresh is proved to be much less than that of the traditional row hidden refresh. Using the hidden refresh method, the 2P2N cells can be designed without considering the ratio of the leakage current of the PMOS access transistors and the NMOS storage transistors. The novel design has the same I/O specification as the SRAM. Moreover, it can be fabricated in standard CMOS process as a small-area embedded memory.