DocumentCode
1807798
Title
Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules
Author
Dillen, Steve J. ; Priore, Don A. ; Horiuchi, Aaron K. ; Naffziger, Samuel D.
Author_Institution
Adv. Micro Devices, Inc., Fort Collins, CO, USA
fYear
2012
fDate
9-12 Sept. 2012
Firstpage
1
Lastpage
4
Abstract
This paper presents the design and implementation of a family of high-performance soft-edge flip-flops (SEF) used in AMD products with core modules code-named “Bulldozer.” We highlight the benefits of the SEF and introduce a new method for comparing flip-flop designs in the presence of clock jitter. We describe an area-efficient level-sensitive scan design (LSSD) implementation in conjunction with supporting clock-gating circuitry for stand-by power reduction. We compare different SEF topologies along with flip-flops from previous designs.
Keywords
clocks; flip-flops; jitter; logic design; microprocessor chips; AMD product; SEF topology; area-efficient level-sensitive scan design; clock jitter; clock-gating circuitry; core modules code-named Bulldozer; flip-flop design; soft-edge flip flop; stand-by power reduction; x86-64 AMD microprocessor; Clocks; Delay; Flip-flops; Jitter; Latches; Logic gates;
fLanguage
English
Publisher
ieee
Conference_Titel
Custom Integrated Circuits Conference (CICC), 2012 IEEE
Conference_Location
San Jose, CA
ISSN
0886-5930
Print_ISBN
978-1-4673-1555-5
Electronic_ISBN
0886-5930
Type
conf
DOI
10.1109/CICC.2012.6330707
Filename
6330707
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