• DocumentCode
    1807856
  • Title

    A 148ps 135mW 64-bit adder with Constant-Delay logic in 65nm CMOS

  • Author

    Chuang, Pierce I-Jen ; Li, David ; Sachdev, Manoj ; Gaudet, Vincent

  • Author_Institution
    Univ. of Waterloo, Waterloo, ON, Canada
  • fYear
    2012
  • fDate
    9-12 Sept. 2012
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A 148ps, single-cycle 64-bit Ling adder with Constant-Delay (CD) logic implemented in the critical path is fabricated in a 65nm, 1V CMOS process. The pre-evaluation and constant delay (regardless of the logic expressions) features of CD logic makes it up to 2X faster than dynamic logic in realizing complex logic functions such as addition. At 1V supply, this adder´s worst-case measured power and leakage power are 135mW and 0.22mW, respectively.
  • Keywords
    CMOS logic circuits; adders; CD logic; CMOS process; complex logic functions; constant delay; constant-delay logic; critical path; dynamic logic; logic expressions; power 135 mW; single-cycle Ling adder; size 65 nm; word length 64 bit; Adders; Delay; Logic gates; Semiconductor device measurement; Transistors; Vegetation;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Custom Integrated Circuits Conference (CICC), 2012 IEEE
  • Conference_Location
    San Jose, CA
  • ISSN
    0886-5930
  • Print_ISBN
    978-1-4673-1555-5
  • Electronic_ISBN
    0886-5930
  • Type

    conf

  • DOI
    10.1109/CICC.2012.6330709
  • Filename
    6330709
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1807856