Title :
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains
Author :
Muramatsu, Atsushi ; Yasufuku, Tadashi ; Nomura, Masahiro ; Takamiya, Makoto ; Shinohara, Hirofumi ; Sakurai, Takayasu
Author_Institution :
Semicond. Technol. Acad. Res. Center, Yokohama, Japan
Abstract :
Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations within a functional block are compensated by the fine-grained supply voltage (VDD) control to minimize power at fixed clock frequency. In the 40-nm test chips, the layout of a data encryption core is divided into 6×7 voltage domains. Both high VDD (VDDH) and low VDD (VDDL) are supplied to each power domain and either VDDH or VDDL is adaptively selected according to the setup error warning signals generated by canary flip-flops. Compared with the conventional single VDD operation, the proposed FADVC reduced the power by 12% at 1-MHz clock in the measurement.
Keywords :
CMOS logic circuits; cryptography; flip-flops; low-power electronics; voltage control; CMOS logic circuit; VDDH; VDDL; canary flip-flop; data encryption core; error warning signal; fine-grained adaptive dual supply voltage control; fine-grained supply voltage control; frequency 1 MHz; functional block; power reduction; size 40 nm; Automatic voltage control; Clocks; Delay; Layout; Power measurement; Voltage measurement;
Conference_Titel :
ESSCIRC (ESSCIRC), 2011 Proceedings of the
Conference_Location :
Helsinki
Print_ISBN :
978-1-4577-0703-2
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2011.6044897