12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains

Within-functional-block fine-grained adaptive dual supply voltage control (FADVC) is proposed to reduce the power of CMOS logic circuits. Both process and design variations within a functional block are compensated by the fine-grained supply voltage (V_DD) control to minimize power at fixed clock frequency. In the 40-nm test chips, the layout of a data encryption core is divided into 6×7 voltage domains. Both high V_DD (V_DDH) and low V_DD (V_DDL) are supplied to each power domain and either V_DDH or V_DDL is adaptively selected according to the setup error warning signals generated by canary flip-flops. Compared with the conventional single V_DD operation, the proposed FADVC reduced the power by 12% at 1-MHz clock in the measurement.